[libre-riscv-dev] [Bug 215] evaluate minerva for base in libre-soc

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=215

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)
> will need adjusting to make the datapath between the core and L1 wider --
> 64-bit at the very least, 128-bit or wider preferred.

yes.  four LD/STs @ 32-bit is the minimum viable data width to the L1 cache,
realistically.  preferably four LD/STs @ 64 bit.

this is a monster we're designing!

address widths also need to be updated: i'm going to suggest parameterising
them because we might not have time to do an MMU (compliant with the
POWER ISA), just have to see how it goes.

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