[libre-riscv-dev] [Bug 215] New: evaluate minerva for base in libre-soc

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 11 14:31:19 GMT 2020


            Bug ID: 215
           Summary: evaluate minerva for base in libre-soc
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---


looks really good: clean design, uses wishbone to the L1 caches and
to the main core.  this will help when it comes to adding SMP down
the line.  the decoder is also very clean.

the only non-obvious bit is how the core works, with source/sink
being created in class "Stage" (which is fine), and with the
inter-transfer layouts being the same (source on previous stage
equals sink on the next stage), that's obvious: the bit that's
not obvious is what-gets-connected-to-what.

i think this is because "sinks" are set up at the start of core.py
whilst "sources" are set up much further down.  in the libre-soc
pipeline code, the layouts are done via objects, and the modules
"take care" of placing data into the "output" inherently.  here,
it's messy, and the separation makes understanding difficult.

other than that, though, it's pretty damn good.

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