[libre-riscv-dev] [Bug 206] Implement branch prediction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=206

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
from ericp, comp.arch:

FYI I stumbled across this masters thesis the other day.
It gives a detailed design for a RISC-V front end with branch
prediction, including wiring diagrams and handshake signals,
with performance simulation results.

Design of the frontend for LEN5,
a RISC-V Out-of-Order processor, 2018
https://webthesis.biblio.polito.it/13198/1/tesi.pdf

and what appears to be the SystemVerilog for the project:

http://webthesis.biblio.polito.it/13198/2/allegati.zip

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