[libre-riscv-dev] [Bug 206] Implement branch prediction

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Mar 7 16:00:25 GMT 2020


--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
from ericp, comp.arch:

FYI I stumbled across this masters thesis the other day.
It gives a detailed design for a RISC-V front end with branch
prediction, including wiring diagrams and handshake signals,
with performance simulation results.

Design of the frontend for LEN5,
a RISC-V Out-of-Order processor, 2018

and what appears to be the SystemVerilog for the project:


You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list