[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #52)

> I see now. So instead of passing in the bit selection and csv name, we'd
> pass in a list of bit selections and csvs,

yes.  and that includes width, and the *list* becomes the (almost only)
argument to PowerDecoder.

the width per PowerDecoder list element (a new namedtuple called Decoder?)
has to be added because it specifies the width of the Switch statement.

> and it would cascade to the next
> csv if the first one doesn't match?

or, just... they're all done in parallel, and we assume that there are no
overlaps.  actually, hmmm, probably a cascade is safer, althought it would
introduce _another_ gate delay *sigh*.

i think we can get away with assuming that the list-of-matches are unique
even though they would be in separate switch statements.

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