[libre-riscv-dev] [Bug 207] Design Rust-based HDL like nmigen (deferred for later)

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 4 08:51:14 GMT 2020


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> (In reply to Samuel Falvo II from email)
> Most of the benefit I can see is not actually the algebraic sum (enum/union)
> types, but actually Rust's generics, trait system, compile-time function
> evaluation (const fn -- like C++ constexpr), and const-generics (generics
> based on values rather than types).

there are a couple of ways to do this.  the first is just to have Signals,
Muxes, Ifs etc and to create an AST in memory, just like in nmigen.

on *top* of that can be considered the addition of data types, such that, just
as in BSV, a bool type can *not* be assigned to a 1-bit Signal, nor can one
signal of one width be assigned to one of another width, you *must* do an
explicit slice.

clocks, reset and cross-domain data transfer was particularly irksome in BSV,
particularly when trying to assign a dual role GPIO pin to be a clock output
for one pinmux selection and a plain GPIO for another.

getting this right *without* the tool being an absolute ftickin nuisance that
just makes you wish you'd never started down this path needs a careful balance.

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