[libre-riscv-dev] [Bug 206] Implement branch prediction

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 3 01:32:10 GMT 2020


--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> now i'm lost.  and need to understand.
> <snip>
> this gives the *appearance* of reversion, rather than "undoing damaged
> register files and memory locations by way of quotes reverting quotes
> *actual* register writes etc." because those writes were *never permitted
> to take place in the first place*.

(second time writing this all, my text editor crashed on my phone)

What's reverted is the branch predictor's logical internal state (as well as
the fetch PC and branch target buffer), not all the registers and memory
locations that are written to.

Oversimplified Diagram:

Branch Predictor/BTB  <----+
   |                       |
   v                       |
Fetch <--------------------+
   |                       |
   v                       |
Decode <-------------------+
   |                       |
   v                       |
Issue Queue <--------------+
   |    ^                  |
   v    |                  |
6600 Scheduler <-----------+
   |     ^   ^             |
   |     |   |             |
   +--> ALU  |             |
   |         |             |
   +--> Load/Store         |
   |                       |
   +--> Branch Execution --+

The branch predictor is logically separate from the branch execution unit --
the branch predictor is part of the fetch pipeline, while the branch execution
unit is after the 6600 OoO engine has a chance to schedule and manage the
instructions, which can only happen after the fetch pipeline gives the OoO
engine the required instructions.

Basically, the 6600 OoO engine can only manage speculative execution of the
instructions it's in charge of, where the fetch pipeline is in charge of
instructions that haven't yet reached the OoO engine, so the fetch pipeline has
to be able to cancel instructions that were erroneously fetched. Part of
canceling instructions is reverting the state of the branch predictor such that
those erroneously fetched instructions don't show up in the branch predictor's
logical state and the correct result of branch execution shows up instead.

Hopefully this all makes more sense.

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