[libre-riscv-dev] [Bug 202] New: potential changes to LibreSOC HDL to suit coriolis2

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=202

            Bug ID: 202
           Summary: potential changes to LibreSOC HDL to suit coriolis2
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Hardware Layout
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

coriolis2 layout expects some specific rules regarding connections between
Cells. it has sometimes been the case that only when seeing a layout is it
discovered that there is a mistake or it is suboptimal. a redesign of the
nmigen HDL would be needed.

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