[libre-riscv-dev] [Bug 199] New: Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=199

            Bug ID: 199
           Summary: Layout using coriolis2 main core, 180nm
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Hardware Layout
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

do layout for single-core 180nm ASIC including 1st level cache.
also peripherals: minimum priority is SDRAM 32 bit, 16550 UART, JTAG and SPI.
secondary priorities are 64 bit SDRAM, GPIO, PWM, EINT, QSPI, SDMMC, RGBTTL,
I2C and the pinmux.
package is to be QFP, maximum around 200 pins only including power and ground.

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