[libre-riscv-dev] ecp5 devboards

[Immanuel, Yehowshua U]

On Mar 1, 2020, at 10:26 PM, Luke Kenneth Casson Leighton <lkcl at lkcl.net<mailto:lkcl at lkcl.net>> wrote:

http://radiona.org/ulx3s/

i think we need some of these.  they are very cute :)

and also have SDRAM which means we can test that out in an FPGA before
doing the 180nm ASIC.

thoughts?

Absolutely. I actually have the VersaECP5 and use LiteX on it quite regularly.
See https://bracketmaster.github.io/MAERI-RTL/main_presentation/_static/maeri_on_fpga_from_concept_to_conception.html#/27

and
https://yehowshuaimmanuel.com/fpga/migen/ethernet_ecp5/

One thing to consider is don’t we need an SDRAM controller?
I guess will have to write  that in Migen - SDRAM isn’t too hard…
Performant controller however is a little more tricky…

Yehowshua