[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #146 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
okaaay, jean-paul, are you ready? i did it... :)

so, here's the steps, you can see in (badly-named) ringoscillator.py
in experiment5

* do a full etesian-and-katana place-and-route on add.vst to create add.ap

* likewise for sub.ap

* do a logical load/save on alu_hier.vst and save alu_hier.ap

* take a **COPY** of alu_hier.ap, called alu_hier_altered.ap and REPLACE
  the word "alu_hier" with "alu_hier_altered".

* take a **MANUAL** copy of alu_hier.vst (because i couldn't work out
  how to use alliance to do the following), and **REMOVE** subckt_48_add
  and subctk_49_sub from the VHDL, and save the results to alu_hier_altered.vst

* load alu_hier_altered.ap/vst and run Etesian place().  save.

* take a **COPY** of alu_hier_altered.ap, REPLACE the word "alu_hier_altered" 
  with "alu_hier_altered2" and save as alu_hier_altered2.ap

* take a copy of the **ORIGINAL** alu_hier.**VST** file, replace the word
  "alu_hier" with "alu_hier_altered2", and save as alu_hier_altered2.**VST**

* load alu_hier_altered2.ap/vst and run a *MANUAL* place on subckt_48_add
  and subckt_49_sub.  save the result

* load alu_hier_altered2.ap/vst and run the katana global router

ta-daaaa

*this* does what i want, in full, and successfully.

why does it work?

* the Etesian.place() will only place "all items" rather than
  "some selected items"

* therefore, to "solve" that, i *REMOVED* the two blocks (subckt_48_add
  and subckt_49_sub) from the *actual VHDL* file, such that Etesian.place()
  did not even know that they exist.

* then, by *reassociating* the resultant (successfully-placed) .ap file with
  a VHDL file that *does* know about the add and sub block, i was able to do
  the *manual* placement.

* also, as an added bonus, the global router recognised that there were
  tracks in the alu_hier.ap which had not been routed yet, and successfully
  connected them.  which was coincidentally exactly what i wanted.

so!... :)

i had to do the file-copying because AllianceFramework._catalog is a global.
there is unfortunately no detection of file-modification, so in a previous
iteration of the code, when i overwrote alu_hier.ap (copying alu_hier_altered
over the top of it), the catalog in crlcore/src/ccore/AllianceFramework.cpp
*did not notice*, and went:

"oh i wrote that out for you once already, you called
 AllianceFramework.getCell() again? i'm sorry, i am going
 to give you the *OLD* version because it's in _catalog".

so, a stat() on the vst and ap files would be a good idea, here, to
check if they've been modified.

secondly: the way to avoid this entirely would be to have a way to
specify, to Etesian.place(), that certain items are simply *not* to
be included for placement.

a more extensive version of that would be to pass in a list of
items that *are* to be placed.

but, for now, success!  it's a mess, but it works.

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