[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=155

--- Comment #12 from Jacob Lifshay <programmerjake at gmail.com> ---
For the 28nm SoC, it would be nice (but isn't required) to be able to adjust
the core clock in small increments (step size of 100MHz or less) and be able to
run up above 2.5GHz since those are useful for overclocking.

Additionally, for less niche use cases, the small step size makes lower clock
speeds for lower-power modes nicer to use, since there is a more varied choice.

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