[libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

paul, benjamin, mikey: i have a huge favour to ask of you (or a "howto"
question), given that i never done VHDL programming before.

thank to florent of enjoy-digital's help, libresoc now has connectivity to
litex in simulation, just like in microwatt.  in particular he added a
"Display" option on any wishbone activity requested by (either) core,
allowing me to see what is going on.

i was therefore looking to do cycle-accurate side by side comparisons, spot
the discrepancies, fix the bug and move on to the next one.

this technique has worked extremely well up to now by comparing against
qemu, and against our python simulator.

we would like to be able to add microwatt to that list.

the problem is that microwatt has branch prediction, L1 cacheing and
pipeline latency all of which mean that i am completely guessing about what
caused any given bus read/write.

any kind of side-by-side comparison of log files, looking for the "one
instruction that does something different/wrong" is out of the question.

... *unless*... there is a "mode" for microwatt that is effectively
equivalent to gdb single-step.

we need a way to stop microwatt from doing any kind of overlapping
instructions.  this *may* be possible already through the JTAG/debug
interface, i do not know.

the alternative is some minor modifications that throw in a deliberate 10
to 20 cycle delay in the instruction issue phase.  this would give ample
time to inspect the internal state (regfiles, PC, SPRs, etc) looking for
discrepancies when running the exact same binary.

what would you suggest here? how can we "single-step" microwatt?  clearly
performance is not important: cycle-accurate comparisons is the goal.

with thanks, and understanding that you are busy people,

l.



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