[libre-riscv-dev] daily kan-ban update 23jul2020

[Luke Kenneth Casson Leighton]

tasks:

https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yestersday:

* went through trap review with samuel.  lots of improvements and bugs fixed
* talked with florian about litex integration. got "compile" but vcd is
problematic

today:

* found that running vcd2fst "fixes" gtkwave problem, allowing debugging of
LibreSOC under verilator litex sim
* started investigating 32/64 bit wishbone mismatch in litex sim

so this is a big deal: getting litex sim working is a first step to being
able to connect to a UART, which in turn will allow running the
"helloworld" and other microwatt examples properly.

next on the list will be adding support for counter SORs, then XICS and
then possibly a RADIX MMU, at which point we can run a linux kernel.

l.



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