[libre-riscv-dev] daily kan-ban update, 22jul2020

[Jacob Lifshay]

today:
still working on Div FSM -- I think it's complete (except for not
supporting cancellation), but didn't thoroughly test it yet. In the
process of refactoring test_pipe_caller.py into a easier-to-test shape
and adding parallel test cases for DivPipeCore, FSMDivCore, and
SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 /
0x32867d69), the pipeline (SimOnly) is giving the correct results
(rt=0x3), it's the ISA simulator code that's messed up
(rt=0xFFFFFFFF).

Luke (or whoever is more familiar with it), I'll let you figure out
how to fix the ISA simulator.

Jacob