[libre-riscv-dev] daily kan-ban update 17jul2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jul 19 12:13:54 BST 2020
On Sun, Jul 19, 2020 at 8:04 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> > > However, when I try to wire them up in a simple synchronous fsm
> > > (soc.fu.div.test.test_fsm.TestDivState.test_div_state_fsm), it doesn't
> > > seem to work: I think the simulation process I made that checks
> > > outputs is somehow getting desynchronized from the process that
> > > toggles inputs -- I added some extra wires that the check process
> > > toggles.
> I'm specifically using Delay to delay a fraction of a clock cycle after
> each Tick before measuring values, so Settle shouldn't be necessary.
hmm don't know what to suggest, then, other than saying "nuts to the
lot of it" and cookie-cutting microwatt divider.vhdl - into a new
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