[libre-riscv-dev] Markdown on the wiki?
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Jul 15 18:12:51 BST 2020
i updated the page you started, a bit more, this morning. you should be
getting the impression now as to why i described this pipeline as dead
simple to start from, because the code itself in spr main_stage.py really
does not actually do very much.
no regfile reading, no decisions, no instruction decoding: nothing. its
*sole* job is to process its inputs and create some outputs. it doesn't
even know which registers that data actually comes from or goes to because
*that is not its responsibility*.
thanks to the pipeline API it doesn't even need to know a thing about
pipelines or even how those are set up: you noted that stages are all
all pipelines are designed this way, as pure combinatorial blocks.
therefore, the formal proofs for each stage are correspondingly trivial in
as you are discovering, the context *around* each pipeline is pretty
involved, especially when you compare it to e.g. Minerva, which is the main
other nmigen core around.
however Minerva is designed as a low performance 32 bit single issue
processor, where this is a high performance multi-issue parallel processor
with OoO instruction order preservation. data paths in Minerva are 32 bit,
addresses are 32 bit: we have a massive **256** bit wide data path and will
be doing at least a 48 bit physical address space.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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