[libre-riscv-dev] daily kan-ban update 09jul2020

[Luke Kenneth Casson Leighton]

On Fri, Jul 10, 2020 at 6:59 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Fri, Jul 10, 2020, 10:26 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Friday, July 10, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > yes with you now.  sorry took a while.
> >
>
> opened a bug report:
> https://github.com/nmigen/nmigen/issues/429

ok let's double-check it.  this pipe_start: (yosys read_ilang
div_simulator.py; show pipe_start):
https://ftp.libre-soc.org/2020-07-10_21-18.png

the chain is therefore (starting from fu/div/pipeline.py):

* DivBasePipe: pipe_start of type DivStagesStart

* DivStagesStart contains
 -        alu_input = DivMulInputStage(self.pspec)
 -      div_setup = DivSetupStage(self.pspec)
 -      core_setup = DivCoreSetupStage(self.pspec)

* DivMulInputStage has a default submodule name of "input"
* DivSetupStage gives its name as "setup_stage"
* DivCoreSetupStage gives its name as "core_setup_stage"

so because DivStagesStart chains those three together, we can confirm
that the input and output parameters - ra, rb, xer_so - are expected
to be copied through in that order.

this from visual inspection of the image, above, is confirmed.  taking ra (only)

* ra starts from pipe_start on the bottom left, gets named input_ra,
goes into input
* comes out of input as input_ra_42, gets named setup_stage_ra, goes
into setup_stage

so we expect

* gtkwave examination of input's ra to be non-zero
* input's ra$1 (which is the *output* from that module) to be non-zeri
* setup_stage's ra to be non-zero
* setup_stage's ra output to... well... exist.  and it doesn't
(because of the missing patch)

ok.  so in this comment:
https://github.com/nmigen/nmigen/issues/429#issuecomment-656814447

you're finding that ra is zero when (and i can confirm here that it is
non-zero) it's expected to be non-zero.

here's where the discrepancy exists: i *am* seeing non-zero values for
top.alu.pipe_start.setup_stage.ra

that's with everything updated on libre-soc side and with this nmigen checkout:
commit 303ea18cb60567e45a755c6b6289a601f27d46e6 (HEAD -> master,
origin/master, origin/HEAD)
Author: Alan Green <alan.green at gmail.com>
Date:   Tue Jun 23 22:12:02 2020 +1000

i've placed a copy of the div_pipeline.il and div_simulator.vcd here:
https://ftp.libre-soc.org/div_pipeline.tgz

l.