[libre-riscv-dev] 130nm for the hackers : finally a reality ?
staf at fibraservi.eu
Fri Jul 3 10:05:26 BST 2020
Luke Kenneth Casson Leighton schreef op do 02-07-2020 om 15:06 [+0100]:
> in other words in order to save time not duplicating all of that work
> involving the compilers, firmware etc, the following strategy might work:
> * define the IOs in mnigen and add them as "foreign instance"
> peripherals... to litex
> * create a core.py again as a foreign instance (in nmigen)
> * when creating a soc.py pull in the foreign IOs and link them to the core.
> i *believe* this has actually been done before, in particular for pulling
> in verilog opencores peripherals, so it is not out of the ordinary.
I think a better approach would be:
- Get libre-riscv core as external in litex and combine it with
- Run full litex sweat, adapt flow to not do P&R and generate a top in
verilog without any IO blocks.
- Integrate this verilog top in nmigen with the IO and do place-and-
route with coriolis from there.
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