[libre-riscv-dev] 180nm ASIC layout image 02jun2020

[Luke Kenneth Casson Leighton]

https://libre-soc.org/180nm_Oct2020/2020-07-02_19-01.png

this is with trap, alu, logical, branch, ldst.  1/4 to 1/3 of the
space (left hand side) is taken up with the INT regfile (it's
addressed in unary, is multi-ported, and cannot use an SRAM).

i'm currently investigating adding div.

l.

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68