[libre-riscv-dev] 130nm for the hackers : finally a reality ?

[Luke Kenneth Casson Leighton]

On Thu, Jul 2, 2020 at 12:04 PM Staf Verhaegen <staf at fibraservi.eu> wrote:

> Is there already a design with mixed litex and nmigen code ?
> If so, it would save me from reinventing the wheel for the Retro-uC.

i've been looking for one: what i've found so far is this:
https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/examples/simplesoc_ecp5.py

litex however is migen (legacy), and my feeling is that to get it to
properly work you need to "back down" to a common denominator, which
is convert everything to verilog (or ilang) and, if doing simulations,
run verilator (or now cxxrtl).

in other words i believe in order to use litex you kinda have to treat
nmigen as a foreign architecture (vhdl, verilog) just like it's done
with any other soc such as microwatt, vexrisc and so on.

looking at litex_setup.py it has both minerva and microwatt as build
options.  it *should* be a matter of examining
litex/soc/cores/cpu/{minerva/microwatt}/core.py and going from there.

i will be finding out shortly.

l.