[libre-riscv-dev] [Bug 193] New: GatedBitReverse can be simpler

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=193

            Bug ID: 193
           Summary: GatedBitReverse can be simpler
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

https://github.com/lambdaconcept/minerva/blob/master/minerva/units/shifter.py#L27

found something that can simplify this:

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_shift/bitrev.py;hb=HEAD

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