[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #32)
> I'm moving the enums for each field in the table to a separate file.

great.

> Would it be acceptable to do a `from power_enums import *` in the decoder and
> testbench?

no, it's really not a good idea.  grep'd "class power_enum.py >f ",
did a bit of vim voodoo, created this:

from soc.decode.power_enums import (Function,
InternalOp,
In1Sel,
In2Sel,
In3Sel,
OutSel,
LdstLen,
RC,
CryIn,
)

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