[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #26)
> (In reply to Luke Kenneth Casson Leighton from comment #25)
> > https://libre-riscv.org/openpower/isatables/
> > using anton's decode1.vhdl, just for laughs i extracted the major opcodes
> > into a csv file.
> 
> I've got something in
> http://git.libre-riscv.org/?p=soc.git;a=blob;f=src/decoder/
> power_major_decoder.py;h=0e0f1f22e5f9d1a92d8362f49cdb6b62c42b0ec4;hb=HEAD

that was quick and pretty ridiculously easy, wasn't it? :)

> I had to modify your table a little bit to remove the spaces after the
> commas. Would it break the display if I did the same thing to the wiki one?

heck no, the whole point is to be able to do wget on the wiki version
(rather than have two out-of-date copies)

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