[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|Create decoder for SOC      |Create decoder for SOC:
                   |                            |Power ISA and RISC-V

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-riscv.org/openpower/isatables/
using anton's decode1.vhdl, just for laughs i extracted the major opcodes
into a csv file.

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