[libre-riscv-dev] Power ISA and associated Challenges

[Luke Kenneth Casson Leighton]

On Sat, Feb 29, 2020 at 3:59 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:

> So recently, it has come to my attention that the Power ISA is quite large.

if you do the full 3.0 ISA which includes an extremely powerful vector
extension - yes.  however we're not going to do that.

we'll do 2.07 (or so) because that's what's under the OpenPower EULA,
and then look at adding the various 3D and Video instructions we need.


> We should itemize its characteristics - just at least so I can get an
> idea of labor involved for future cost analysis...
>
>
>   - How many instructions

not that many, if you look at anton's code (below) - there are quite a
few "sub-options" (add-immediate, add-with-carry and so on) which make
it look like there are a lot.

>   - What is the minimal viable subset of the ISA we must support

2.07 or so.

>   - I hear the decoder is more complex - why?

mmm not really:
https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl
https://github.com/antonblanchard/microwatt/blob/master/decode2.vhdl

you can see it does a form of escape-sequencing from the "major"
opcodes.  opcodes 19, 30, 31, 58 and 62 are "sub-decoded" further.  i
wouldn't say 400 lines of VHDL, almost all of which is tables, is
"complex".


>   - How does complexity overall compare with RISCV

it's a little more, but not enormously so.  IEEE754 FP has a few more
rounding modes; it also has "carry" on integer arithmetic, which is a
good thing for constructing larger (longer) bit-length operations.

when it comes to SimpleV however, carry flags is going to be a bit of
a pain.  not a total pain, just a nuisance, because rather than being
a *single* flag, the carry-in and carry-out have to be a *vector* of
bits, one per element in the vector.

that's not insurmountable.

l.