[libre-riscv-dev] [Bug 189] Create partitioned right shift using the existing partitioned left shift

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Feb 27 22:27:22 GMT 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #7)

> Rol ra, rb, rc getting translated to
> shl tmp1, rb, rc
> shr tmp2, rb, (32-rc)
> or  ra, tmp1, tmp2
> should be constant time with respect to the data being manipulated. 

so there are a couple ways to do the micro-coding, one of them being to
have "spare" inputs (extra Function Units) to the pipelines, which
the normal instruction issue engine does not have access to.

the output from the shl (tmp1) goes into an *extra* FU operand 1 on an OR pipe.
the output tmp2 goes into the operand2 of the OR pipeline's extra FU.

finally the output from the OR goes into ra, in the *normal* result system.

it's basically hard-coded micro-code, rather than "programmable" micro-code.

> The
> actual timing probably depends on what else is in the pipe, but that's true
> of other instructions as well.

please, nobody mention spectre or other timing-related attacks.  sigh.

basically in the above example, if you do enough OR operations, shr or
shl operations, you can tell statistically how many ROR operations there are.

it's... information leakage, and the only way to stop it is to have more
resources available than can be issued.

in any combination.

i am not hugely keen on doing that kind of analysis at this stage!

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