[libre-riscv-dev] [Bug 189] Create partitioned right shift using the existing partitioned left shift

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=189

--- Comment #4 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> Created attachment 27 [details]
> screenshot of yosys (2)
> 
> ah, nice.  see how the cascade is no longer an O(N^2) thing?
> just a simple O(N) one instead.

Ah yes I see now. However it looks like yosys is able to optimize the first
version into the second one, they both end up as the same number of gates.

> 
> next one, ROR? :)  or shall we leave that one to be a
> micro-op, put data twice through the pipelines as a
> FSM?  hmm, back to the other bugreport i think

ROR shouldn't be as common as SHL and SHR in normal code right? I think doing
it in microcode would be fine, at least for the first iteration.

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