[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #130 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #129)
> these blocks we *know* in advance, they are *only* connected by register
> latches.

If we are naming things anyway this is called a datapath in the industry.

Problem I see with using datapath layout is that typically the input of the
datapath comes from the register file and also the output has to go to the
register file. So if you go always left to right one of the sides will be far
away from the register file. For smaller technology nodes the capacitive load
of these long paths will be a killer for performance.
This problem is more pronounced if you have different functional blocks where
for all the blocks the input and output is coming from and going to the
register file.

Using an analytic placer will naturally get both the input and outputs close
the register file and move the middle of the path further away minimizing extra
delay from the interconnects.

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