[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #126 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #125)
> (In reply to Jean-Paul.Chaput from comment #124)

OK I see your vision of hierarchical P&R.

* The bottom up assembly approach is completely legitimate for the
  netlists.

* For the layout, less so. I reason along the same lines as Staf, but
  maybe less radically (or I'm lagging behind).

  * If you break your design in too tiny blocks you will prevent
    the placer to perform some placement optimization. So, in
    my opinion you should have one or two level of hierarchy in
    the layout placement.
      The top level floorplan (full chip) and maybe a supplemental
    one in big top-level sub-blocks.
      Staf recommend to do it completely flat (his arguments makes
    perfect sense, but I need to see it by myself).

  * Another argument is that I'm not sure that Coriolis will handle
    well (or in reasonnable time) blocks of more than 100K gates.
    So your approach is important at least as "backup plan".

  * Still another point to consider is how much "block layout" reuse
    do you have ? Sub-block layout may be interesting if you have
    one block used multiple time that can have the same form factor
    and pin positions.

Anyway there is always a lot of tradeoff in that stage of a design.
Ideally you should make a check for all three of them, at least on
significant part of the design.

Now, for the technical part of recursively building layout with
Coriolis:

* The placer can only handle cells. So only the "leaf" netlists can
  be done by him.

* Do not put blocks in libraries, that would confuse some Alliance
  tools that would see them as "terminal black boxes".

* To assemble placed layout you must write Python scripts. They are
  not complicated once you know what to do, but still, it implies
  that *you* know beforehand how the blocks must be placeds.
  This is *automated* *manual* floorplan.
    You can even develop a Python program to furhter ease the
  automation.

There are still questions left open:

* Should we place the whole chip (whatever the method) then route
  in one go. This may avoid the creation of channel routing.

* Or should we route each sub-block as we go up. Which may allow to
  create guard ring, but will need the creation of routing channels,
  and place the external terminals of the blocks.

All of the above are difficult questions, even so because the answer
may emerge only after starting to implement.

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