[libre-riscv-dev] Possible memory related paper and rust

Samuel Falvo II sam.falvo at gmail.com
Wed Feb 26 03:38:17 GMT 2020

On Tue, Feb 25, 2020 at 6:20 PM Jacob Lifshay <programmerjake at gmail.com>

> It seems interesting but probably not useful for our design, since it seems
> to be about microcontroller-type designs where they are using two sram
> ports instead of one and switching the design to be completely single-cycle
> instead of using the traditional 5-stage RISC pipeline. Those modifications

It looks like the processor is a classic asynchronous logic design that
happens to use Harvard architecture and *in-core* memory for the
instruction store (which is how single-"cycle" performance is achieved).  I
don't see what's actually new design-wise, otherwise.  It IS interesting to
see the performance figures though, and I'm happy that interest in
asynchronous logic (especially in FPGAs) is still a thing.  I'm a big fan
of async logic.

Thanks for mentioning this!

Samuel A. Falvo II

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