[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #119 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #115)

> Got it. In your coriolis2/settings.py, allow a more wide range
> of clock signal names:
> 
> env.setCLOCK( 'clk|ck|cki' )
> 
> The clock signal/terminal inside the I/O pads is named "ck" and was not
> recognized as a clock, so it wasn't routed, hence all the clock
> of the pads (in the ring) got disconnected.

ee!  it worked!

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