[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #115 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Jean-Paul.Chaput from comment #98)
> (In reply to Luke Kenneth Casson Leighton from comment #95)
> > (In reply to Luke Kenneth Casson Leighton from comment #94)

> > ck of 'b_2' is NOT connected to ck of 'a_3' in netlist 2
> > through signal mbk_sig35 but to signal mbk_sig62
> > 
> > ck of 'b_3' is NOT connected to ck of 'a_3' in netlist 2
> > through signal mbk_sig35 but to signal mbk_sig45
> > 
> > 
> > however "make view" actually works which is a really nice surprise.
> > 
> > it is near-identical to the adder example, both the Makefile and ioring.py
> > any clues?

Got it. In your coriolis2/settings.py, allow a more wide range
of clock signal names:

env.setCLOCK( 'clk|ck|cki' )

The clock signal/terminal inside the I/O pads is named "ck" and was not
recognized as a clock, so it wasn't routed, hence all the clock
of the pads (in the ring) got disconnected.

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