[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #112 from Staf Verhaegen <staf at fibraservi.eu> ---
> oh, Staf: if there is time, are you going to include a PLL in the test
> ASIC in March? (RingOscillator)

We already discussed this. There is no time for me to do it and if somebody
else wants to do the design he needs to get through the TSMC NDA procedure
which I also don't see feasible.

The 0.18um prototype will still run at a frequency where the clock can be
provided externally without the need of a PLL on-chip.

Possible PLL development should be done in a separate project and getting the
0.18um libre-SOC prototype design finished without a PLL should IMHO get
priority.

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