[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #106 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Jean-Paul.Chaput from comment #103)
> (In reply to Staf Verhaegen from comment #102)
> > Alternatively I can also just provided the pin location of signel IO cell
> > and the IO-ring can still be built by the Coriolis scripts.
> 
> Could you provide us with phantoms of the I/O pads?
> Just boxes with terminals at the periphery (the soldering pad,
> the I/O ring pad and the one to/from the core) compatible with
> nsxlib ?

That's actually what I meant; but first plan is to have open source IO cells
and than you will get the Coriolis library with the full design of the cells.

> ah, good word: phantoms.

Actually the term used in the industry is abstract views...

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