[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #101 from Staf Verhaegen <staf at fibraservi.eu> ---
>  Foundries are usually very touchy about the pads and allows only
>  the one they validates. So I assume that Staf will add the pads
>  himself with the ones that TSMC will supply.

Not fully true, foundries will tape anything that does not give DRC violations.
You are fully on your own though if the chip does not perform as expected and
you have deviated from the reference flow. Given that we use a non-qualified
P&R tool we are on our own anyway ;).

I will have test open source IO cells on the test tape-out in May and if
everything goes well these will be used for the libre-SOC prototype tape-out.
But using TSMC ones is a back-up plan though.

So I will make the IO-ring and will provide the location of the pins with input
and output connections to the core. This will be either as LEF or directly as
Coriolis database. I will not take care of connecting the core to the IO cells
though.

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