[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #99 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---


On Monday, February 24, 2020, <bugzilla-daemon at libre-riscv.org> wrote:
http://bugs.libre-riscv.org/show_bug.cgi?id=178


> it is near-identical to the adder example, both the Makefile and ioring.py
> any clues?

  I will take a look. But I think there is no need to try to make
  a full design with pads, only a core.

yeees... except we need to make a dummy one so that the routing on the
floorplan matches the NSEW entry/exit points and order.

in particular, because we are doing a QFP for this test ASIC, and the GND and
VDD are used for EM shielding between GPIO pins that will be up to 150mhz in a
few cases, the bond wires have to go in the right order (they cannot cross
pads)

unlike a BGA which sits on a PCB and the layers sort out any inconvenient mess
of arbitrary exit order.





    Foundries are usually very touchy about the pads and allows only
  the one they validates. So I assume that Staf will add the pads
  himself with the ones that TSMC will supply.
    I know you're reading us Staf ;-)

:)

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