[libre-riscv-dev] DDR PHY
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Feb 24 17:28:06 GMT 2020
On Mon, Feb 24, 2020 at 4:09 PM Cole Poirier <colepoirier at gmail.com> wrote:
> > On Feb 24, 2020, at 7:46 AM, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > EUR 600,000, not EUR 60,000.
> Oh wow that’s really something! Quite close to the budget of a single NLNET grant. What I lovely mistake to have made, now the price seems 10x lower to me than I initially mistakenly thought.
> >> I still am struggling to comprehend what PHY “is”,
> > look it up. PHY. physical. physical interface.
> I try not to write anything to the mailing lists that I haven’t tried to research on my own before hand. I understand that this is a technical mailing list and such behaviour would be unproductive.
no it's fine, that's actually perfectly acceptable: i forgot about
that. if you *can* demonstrate that you've gone to the trouble of
trying to find out for yourself, people on tech lists tend to react
much better precisely because you've demonstrated an independent
desire to find the answer.
> The reason I was asking here is that I have looked it up and tried to research this dozens of times over the past 6 months and still not been able to understand what differentiates PHY from cores.
i searched the words "ASIC PHY" and this came up:
> I actually have not been making judgments and then freezing but have been using the method you describe.
cool! funny thing is, it applies just as well to languages as well as
> With this subject I understood that it literally meant PHYsical layer, but I was unable to progress any further in my understanding than that... until today :) In a nice coincidence, you have actually provided the exact hint I needed on the other LPDDR3/4 mailing list thread. The key understanding I was missing is the difference between digital and *analogue* design.
> It wasn’t that I was stuck, it’s that this was an unknown I’ve kept returning to without being able to progress in my understanding. With my new understanding that analogue design and synthesis is in an entirely different electrical engineering domain and cannot by synthesized from higher level languages like Verilog,
oh... it can: analog *can* be written in HDL.. it's just that the
layout is a bitch, because analog critically depends on many many more
these are circuits, after all. look up circuit design - PCB and
breadboards - it's exactly the same thing, just millions of times
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