[libre-riscv-dev] [Bug 140] Implement AMDVLK / RADV Mesa Vulkan Driver NLNet 2019-10-042

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=140

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Overview

We have the unusual goal of developing not just a new 3D MESA driver:
the hardware itself is being simultaneously developed in conjunction with
the software driver.

However before spending the time implementing full hardware (even in HDL),
which will be emulated significantly slower than actual hardware, we need
to implement - and test and evaluate - the planned instructions using an
emulator, first.  This significantly reduces both development time and
cost, allowing fast iteration and evaluation.

Once we are happy with the chosen hardware instructions at the simulation
level, then we may move to implementing them in hardware.  We will need
to write full unit tests of both the hardware and also run software unit
tests as best as practical on emulated hardware (knowing that it will be
operating thousands to tens of thousands of times slower) and, if practical,
running on an FPGA board.

After the hardware-level simulation, if the gate count and estimated
gate count is acceptable when compared to commercial GPUs, *and* the number
of pixels generated per clock is at an acceptable commercial level,
then we can consider the hardware and software part of the project to be
completed.

Until then, we iterate round the above, and, once completed, finish off
by documenting the hardware instructions as an "ISA Extension" for POWER.

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