[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 09:29:19 GMT 2020


--- Comment #85 from Staf Verhaegen <staf at fibraservi.eu> ---
Reason why the P&R flows have evolved from doing P&R on subbblocks to P&R on
full design is because of the delay caused by the interconnect parasitics.
When scaling, the importance of the interconnect capacitive load becomes the
main cause for delays in a chip and is given anymore by the input gate
capacitance of the cells connected to the path. Therefor timing driven
placement is needed where during placement the capacitive load on the time
critical paths is taken into account. The proprietary tools even have options
to optimize the synthesized logic during placement, e.g. the tool can tranform
the logic on the critical paths in equivalent logic with better delay behavior
for the current design and it's placement.

In a big chip the biggest delay is likely seen on the high fan-out nets
connecting different blocks, e.g. the buses. When doing P&R on the subblocks
and connect the blocks later on a higher level you block the timing driven
optimization of these paths by the placer and you need to do it yourself during
floorplanning and be able to guide the placer.

For the prototype it is not strictly necessary because the effect is that the
chip will only be able to be run at a lower frequency than what one would
predict; my estimate is around 70% of the clock frequency of what is predicted
when not taking the interconnect parasitics into account. But I do hope the
prototype is already used to see how the P&R has to evolve for future scaling.

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