[libre-riscv-dev] DDR PHY

Cole Poirier colepoirier at gmail.com
Mon Feb 24 04:03:13 GMT 2020

> On Feb 23, 2020, at 3:44 PM, Immanuel, Yehowshua U <yimmanuel3 at gatech.edu> wrote:
>> controller. these are usually USD 500,000.
> Which part is 500?
> Would would be designing the PHY on chip?

Luke, in the link you provided (https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master>), I see a controller directory, and several other files in the …/peripherals/sdram directory. Are these other files the ~200 MHz sdram you are referring to?

On a related note, what is the current plan for the DDR PHY after the first tape out, and also the eventual first commercial Libre-SOC production run? Is our current plan what is stated on the mclass/ddr page (https://libre-riscv.org/shakti/m_class/DDR/) "Symbiotic EDA: DDR3 PHY available for $300k?” Additionally, if we are building a *fully libre* soc, is this plan to purchase proprietary (I assume) PHY consistent with these aims and with the charter? Is this one compromise we will have to make in the first iteration because otherwise we will be unable to complete the project on time? Is the PHY fully documented and verifiable (in the security/privacy sense, not necessarily formal sense)? Apologies if this has been previously discussed and I have missed it. If so could you please point me to the relevant mailing list thread or web page? Due to my relative ignorance, I have a question that may be completely beyond the scope of the first production run timeline. What is the technical and time-labour (man-months/years/decades) cost of developing our own DDR3 PHY. From what I’ve found in looking for answers about the nature of PHYsical layers online, my present understanding it that it is also synthesizable with high-level hardware description languages, and appears to have the functionality/constraints of a DSP, or another hard real time processor. I’m really doubtful that my current understanding is correct. Can you please help me understand better?

On an unrelated note, I have been spending a decent amount of my free time trying to get the HDL coriolis2 workflow set up, but having significant difficulties. I’m going to follow up this email, with a comment on the relevant bug report.


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