[libre-riscv-dev] [Bug 140] Implement AMDVLK / RADV Mesa Vulkan Driver NLNet 2019-10-042

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=140

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so 8 months for the first iteration and 8 for two hardware
iterations?

first iteration

* 3 to 4 months software only (SwiftShader style) 3D MESA Driver, portable (x86
etc) using non-accelerated LLVM: EUR 12000
* 2 to 3 months adding iterated support for 3D opcodes to ISA Simulator (and
unit tests): EUR 7000
* 3 to 4 months first iterative effort developing and adding hardware
accelerated 3D opcodes to 3D MESA driver: EUR 12500
* 2nd iteration of opcodes in 3D MESA driver: EUR 12500
* Documentation to the level of an ISA Standards Proposal of all hardware
opcodes: 6000

The list of opcodes includes:

* Transcendentals (SIN, COS, ATAN2, LOG, POW, ROOT), and CORDIC
* Vector ops DOTPRODUCT, HYPOT, CROSSPRODUCT, LERP, SLERP
* MV.X and Swizzle (xyzw)
* Texture opcodes where practical and budget permitting.
* If budget permits, Matrix operations as well.

It is a big list.

Note that YUV2RGB etc are covered by the Video proposal so there is not a
*HARDWARE* budey for them, however they will need a 3D MESA one.

Note also that coordination with Jacob is needed on the LLVM IR development.

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