[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=138

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #5)
> I did have a chat with Jean-Paul and provided him information on the process
> that will be used for the prototype tape-out. He will have a further look to
> see if changes need to be done the coriolis setup.

fantastic that is very helpful.  i asdume it was private because it was under
NDA (because of the TSMC NDA).

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