[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Feb 23 00:12:41 GMT 2020


--- Comment #73 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
okaaay, i have a sneaking suspicion i know what might be going on.
two things:

nmigen allows signals to be declared "zero width".  these
don't do anything, they don't get "actioned", and so on.
however they end up in the yosys output.

secondly: i fixed one of these, replacing it with a module
that assigns a constant to a Signal.  here's the yosys code:

module \sm3
  attribute \src
  wire width 7 output 0 \mask
  wire width 1 $verilog_initial_trigger
  process $group_0
    assign \mask 7'0000000
    assign \mask 7'0000011
    assign $verilog_initial_trigger $verilog_initial_trigger
    sync init
      update $verilog_initial_trigger 1'0

and here's the resultant vst:

entity sm3 is
  port ( vdd : linkage bit
       ; vss : linkage bit
end sm3;

architecture structural of sm3 is


end structural;

note how it's empty?  it also results in sm3.ap not being created.
further on, we end up with "EtesianEngine::toColoquinte() cannot manage
unplaced block, cell height is -2"

(because it's empty)

i also ran into this problem a number of times when i tried to cut out
code (for debugging purposes) by assigning a Const to an output Signal,
expecting the VHDL in that Cell to simply hard-set the output.

however it seems that the result is that no VHDL is generated at *all*.

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