[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Feb 22 14:32:21 GMT 2020


--- Comment #67 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #65)
> btw remember, jeanpaul, we aim to break the layout into blocks (cells)
> hierarchically, anyway, so that if necessary we can reuse some (particularly
> the large FPU ALU blocks) and also do a little more control over routing, as
> well as add in GND VIA rings around blocks.
> so, learning how to do blocks early would be good.

No problem. You should have a look to the RingOscillator bench in
alliance-check-toolkit. Fully manually placed & routed block.
Shows all the technique you can use.

For FPU block, the P&R should be used unless you have a clear idea
of the placement. But from what I know, it is not trivial.
Then with a script, wrap up the whole in a ring of VIAs.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list