[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #65 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
btw remember, jeanpaul, we aim to break the layout into blocks (cells)
hierarchically, anyway, so that if necessary we can reuse some (particularly
the large FPU ALU blocks) and also do a little more control over routing, as
well as add in GND VIA rings around blocks.

so, learning how to do blocks early would be good.

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