[libre-riscv-dev] next tasks

Lauri Kasanen cand at gmx.com
Thu Feb 20 07:39:21 GMT 2020

On Wed, 19 Feb 2020 14:14:16 +0000
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> we only have a few months in which to hang together all of the pieces
> that have been put together, to make a 64-bit 180nm chip.  because
> we're not doing this in verilog i believe it is reasonably doable, if
> we take steps to cut "unnecessary" things out i.e. not do too much.
> chop out L2 cache for example.

What about the C/C++ simulator/interpreter timeline? It's not a blocker
for the hw tapeout, but it is a blocker for my work, which probably
mostly won't make it for the simple Oct tapeout anyway.

- Lauri

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