[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[Jean-Paul Chaput]

On Wed, 2020-02-19 at 22:16 +0000, bugzilla-daemon at libre-riscv.org wrote:
> http://bugs.libre-riscv.org/show_bug.cgi?id=178
> 
> --- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> ok worked out that you have to have signals named "m_clock" and "p_reset"
> 
> now we have...
> 
> 
>      [035] Bipart. HPWL:       4381 RMST:       4717
>            Linear. HPWL:       2155 RMST:       2388
>            Orient. HPWL:       2147 RMST:       2376
>      [036] Bipart. HPWL:       4346 RMST:       4683
>            Linear. HPWL:       2191 RMST:       2429
>   o  Detailed Placement.
>      [000] Oriented ....... HPWL:       3996 RMST:       4361
> 
> [ERROR] Didn't manage to pack a cell: leave more whitespace and avoid macros
> near the right side

  The placer algorithm needs a certain amount of free space to operate.
  On big design 5% of free space is enough to ensure that because that's
  still some space. But on small design like this example this is not
  enough, you have to increase to 7% or 10%.
    This is done in the configuration file "./coriolis2/settings.py",
  look for:

    Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 5.0 )

    The name of the clock signal be changed, it doesn't need to be called
  "m_clock".

    af  = CRL.AllianceFramework.get()
    env = af.getEnvironment()
    env.setCLOCK( '^ck$|m_clock' )

    For "p_reset", that's strange.

    How can I get the design to check it ?

    I'm working on directly integrating nMigen in alliance-check-toolkit.
    I did get the latest nMigen but, on my Debian 9 chroot, it does not
  work because I guess it needs at least Python 3.6 (only 3.5 on Debian).
  But works on CenOS 7 ;-).


>         Python stack trace:
>         #0 in                ScriptMain() at
> .../dist-packages/cumulus/plugins/C
> lockTreePlugin.py:108
> 
>   o  Recursive Save-Cell.
>      + alu_hier (netlist,layout).
> 
-- 

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