[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hi jean-paul, i began compiling part_sig_add.py, ran into
"PortMap::_lookup() unconnected" and tried using alu_hier.py instead
(it's simpler), same issue

[ERROR] PortMap::_lookup() Unconnected <<id:3927 Plug UNCONNECTED ck_htree.i>>.
[ERROR] PortMap::_lookup() Unconnected <<id:3926 Plug UNCONNECTED ck_htree.q>>.
       + sub (netlist,layout).
       + add (netlist,layout).
[ERROR] PortMap::_lookup() Unconnected <<id:3927 Plug UNCONNECTED ck_htree.i>>.
[ERROR] PortMap::_lookup() Unconnected <<id:3926 Plug UNCONNECTED ck_htree.q>>.
mk/pr-coriolis.mk:83: recipe for target 'alu_hier_cts_r.vst' failed
make: [alu_hier_cts_r.vst] Error 1 (ignored)
MBK_OUT_LO=al; export MBK_OUT_LO; MBK_SEPAR='_'; export MBK_SEPAR;
/home/lkcl/alliance/install/bin/cougar       -c -f alu_hier_cts_r
alu_hier_cts_r_ext

looking through the errors:

[ERROR] CParsVst() VHDL Parser - File:<./alu_hier.vst> Line:254
        Port map assignment discrepency instance:0 vs. model:1
        Python stack trace:
        #0 in                  <module>() at
/home/lkcl/alliance-check-toolkit/bin/doChip.py:320

Traceback (most recent call last):
  File "/home/lkcl/alliance-check-toolkit/bin/doChip.py", line 335, in <module>
    sys.exit( shellSuccess )
NameError: name 'shellSuccess' is not defined
mk/pr-coriolis.mk:83: recipe for target 'alu_hier_cts_r.vst' failed
make: [alu_hier_cts_r.vst] Error 1 (ignored)
MBK_OUT_LO=al; export MBK_OUT_LO; MBK_SEPAR='_'; export MBK_SEPAR;
/home/lkcl/alliance/install/bin/cougar       -c -f alu_hier_cts_r
alu_hier_cts_r_ext


and then at alu_hier.vst:

  ck_htree : buf_x2
  port map ( i   => UNCONNECTED
           , q   => UNCONNECTED
           , vdd => vdd
           , vss => vss
           );

so how do we fix that?  create a clock as part of the output, somehow?

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