[libre-riscv-dev] next tasks
programmerjake at gmail.com
Wed Feb 19 20:56:39 GMT 2020
On Wed, Feb 19, 2020, 12:26 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Wed, Feb 19, 2020 at 8:17 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Immanuel, Yehowshua U schreef op wo 19-02-2020 om 14:24 [+0000]:
> > > Also, do keep in mind that while October is a healthy target, if we
> miss it, its not the end of the world.
> > No, but I do reserve the right to then tape-out a prototype chip with
> > something else on it.
> more than happy with that, staf: i did want to ask you if you wanted
> to include a basic core anyway on the design (i favour the Motorola
> 68000) because we need some sort of "boot and power management core".
I'd recommend something other than the MC68000 that has much wider compiler
support (at least both modern versions of llvm and gcc) as well as a less
unusual ISA. (address registers -- need I say more?)
Also, supporting 64-bit pointers allows sharing address space with the main
processors (more important than the other concerns).
If we don't need any custom extensions, maybe just pick a RV64IMAC core
since the ISA is simple, there's tons of available implementations if we
don't want to build our own, and so we can reduce ISA proliferation on the
SoC that way?
More information about the libre-riscv-dev