Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Wed Feb 19 06:05:53 GMT 2020
So from here: https://libre-riscv.org/3d_gpu/architecture/
The basic principle: the front-end ISA is variable-length Vectorised, with a hardware-level for-loop in front of a predicated SIMD backend suite of ALUs. Instructions issued at the front-end are first SIMD-grouped, then the remaining "elements" (or groups of SIMD'd elements) are thrown at the multi-issue OoO execution engine and the augmented-6600 Matrices left to their own devices.
Um, how many ALUs are we targting?
I like the dependency matrix thing - that’s pretty simple to implement, should be passably performant...
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